The National Technology Roadmap for Semiconductors: Applications of Cost Modeling

Daren L. Dance, VP Technology
Wright Williams & Kelly, Inc.

The National Technology Roadmap for Semiconductors1 (NTRS) has identified many potential applications of cost modeling for the semiconductor industry over the next 15 years. In fact, all of the six "Grand Challenges" summarized in the NTRS identify opportunities for cost modeling:

• Affordable Scaling: "New materials, new technologies, and new approaches must be    invented. Affordable scaling and these required inventions constitute the Grand    Challenges."
• Affordable Lithography at and Below 100 nm: ". . . the solution will require more than    simply developing an exposure tool . . . it will require a complete infrastructure of resists;    masks; mask writing, inspection, and repair tools; and associated systems."
• New Materials and Structures: "Technology generations beyond 100 nm will require either    materials beyond conventional materials and dielectrics or conceptually new approaches    to interconnect."
• G Hz Frequency Operation: "Solutions will require approaching the overall system as a    unit rather than treating design, integrated circuit, and packaging as separate entities."
• Metrology and Test: ". . . it is not clear how the more complex chips of future generations    will be tested. Affordable, sensitive, and accurate methods are required; . . ."
• Research and Development: "The research and development needs and manufacturing    costs for each technology area appear to increase as feature sizes decrease . . . . Stand    alone solutions may neither be affordable or manageable in the future."

The following chart summarizes the cost challenges. Again quoting the NTRS, "The ability to reduce the cost per function by an average 25 -- 30% each year represents one of the unique features of the semiconductor industry."

semiconductor cost per function chart

Click Here to View Enlarged Image

In the following sections, we will look at cost implications in some of the NTRS thrust areas.

Design and Test

Design productivity has made little progress since the 1994 Revision of the NTRS. "The decrease in design productivity will limit the historical rate of cost per function improvement. Design productivity must be increased significantly or the industry's ability to utilize advancements in manufacturing technology will decrease."

Test also remains a serious issue. "Changing processes and design methods are pushing testability beyond economic limits. Rapid improvements must be made to improve overall testability and test economics." The following chart forecasts test system cost:

semiconductor test system costs

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Process Integration, Devices & Structures

Many technical issues face the process designers and integrators. Addressing these will require measurement schemes that, ". . . require major improvements in meteorological tool data volume, feedback time, and cost per measurement."

Maintaining reasonable reliability and fault isolation costs will require developing new tools and methods: • Back-side Fault Isolation Tools
• Higher Resolution Inspection and Probing Tools
• Deprocessing and Microsurgical Tools

Front End Processes

Among the difficult challenges for front end processes is improving the cost of ownership of silicon and other materials. The challenge between now and 2006 is improving silicon quality at reasonable costs. The challenge after 2006 will be fabricating silicon in 450 mm and 675 mm wafer sizes required for 64 Gbit DRAM circuits. "The reduction of the price ratio of epitaxial to polished wafers . . . favors continued use of epitaxial wafer, consistent with the declining fixed cost of ownership for single wafer epitaxial reactors."

In front end processes, "Cost of Ownership (COO) will become more important and must be traded off against performance, quality and yield." Some areas of potential COO improvement mentioned in the NTRS include:

• Reduced chemical use • Water and chemical recycling • Footprint reduction • Fluid flow modeling and optimization • In situ process control


The technical challenges in lithography are compounded by the costs of developing solutions. The NTRS points out, "Cost containment and reduction will require a total systems approach that includes exposure tools, mask, resist and metrology. . . . The cost to develop a single total system solution through to a commercially available tool and infrastructure is expected to approach one billion dollars."


The increased number of metal layers in future processes will place additional emphasis on the COO of interconnect processing and tools. See the following chart.

number of semiconductor metal levels by year

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The transition to copper and other new materials may lead to process simplification but will introduce new cost impacts as well. Many of these new COO impacts will be ESH related, such as:

• Unknown process emissions
• Disposal of potentially hazardous materials
• Use of large volumes of water
• Electroless plating
• Precursor materials
• Global warming gases

The NTRS indicates that, "Approaches to reducing the COO include more extensive use of modeling/simulation in tool design, process monitoring and control and in situ cleans."

Factory Integration

The NTRS lists the following difficult challenges for factory integration:

• Factory Cost
• Operational Effectiveness
• Factory Investment Risk
• Process/Factory Complexity

Improvements in factory productivity and efficiency will be required to keep the semiconductor industry on the historic 25 -- 30% cost learning curve. SEMATECH analysis indicates that the following overall equipment effectiveness (OEE) will be required for bottleneck tools.

overall equipment efficiency (OEE) requirements for semiconductory bottleneck tools

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"These OEE measurements will be complementary to COO and throughput measurements. Improving on all of the operational measurements is a shared responsibility of both the manufacturing companies and the supplier companies." The improvements to COO and OEE will come through:

• Improved software reliability
• Water use reduction
• Power use reduction
• Factory effluent/emissions reduction
• Defect reduction

Assembly & Packaging

A difficult challenge for assembly and packaging is the continued reduction in cost per printed circuit board layer. The NTRS states, "Costs will drive technology tradeoffs for all market segments. . . . Although assembly and packaging costs are expected to decrease over time on a cost per pin basis, the chip and package pin count is increasing more rapidly than cost per pin is decreasing." These trends are illustrated in the following chart:

range of semiconductor packaging and assembly costs per year chart

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Environment, Safety & Health

Meeting the environmental, safety and health challenges may lead to COO reductions in many areas. For example, projected water and power reductions driven by ESH concerns are illustrated in the following chart:

semiconductor fab use of water and power by year chart

Click Here to View Enlarged Image

These trends may lower COO for many semiconductor manufacturing tools.

Defect Reduction

Defect reduction and yield improvement remain important cornerstones of the drive to reduce manufacturing costs and COO. Yield improvement will need to address increased circuit size, smaller critical defect size, and more masking levels. These trends are summarized in the following chart:

semiconductor defect density and faults per mask layer chart

Click Here to View Enlarged Image

Thus, increases in interconnection requirements which are reflected in the NTRS number of masking layers are driving fault density reductions at a faster rate than even the aggressive circuit and device sizes.


Cost issues for metrology raise an interesting infrastructure issue, "Many metrology suppliers are small companies that find the cost of providing new tools for leading-edge activities . . . prohibitive. The initial sales of metrology tools is to tool and process developers. Sustained, high-volume sales . . . does not occur until several years later. The present infrastructure cannot support this delay." This issue is not limited to metrology suppliers but is an issue for all new, innovative companies entering the industry.

Meeting the Industry Challenge

Wright Williams & Kelly, Inc. provides a comprehensive suite of operational modeling solutions ranging from focused process to high level factory analysis tools. These tools are useful in meeting the industry's cost challenges as identified by the NTRS. Semiconductor industry suppliers and manufacturers will follow many paths to meeting industry needs for the next fifteen years. These include:

• Upgrading factories
• Building new factories
• Extending tool designs
• Retrofitting existing tools
• Designing new tools
• Developing new applications for existing materials
• Developing new materials

Modeling and simulation will foster decisions that reduce risk and increase the reward. The following table indicates how WWK decision solutions can address the issues identified by the NTRS.

Factory Commander®
Factory Explorer®
Tool Description
COO for Equipment and Process Steps
COO for Process Flow Sequences
Factory Level Cost and Resource Model
Capacity, Cost and Simulation Analysis
NTRS Issue
Affordable Lithography
Mask and process equipment COO
Mask making processes
Factory integration
Capacity/cost analysis and optimization
Affordable Scaling
Equipment scaling
Process Scaling
Integrating wafer fab and assembly costs
Factory scaling and optimization
Assembly & Packaging
Equipment COO
Process COO
Integrating wafer fab and assembly costs
Capacity/cost analysis and optimization
Cost of Ownership
Tool and material impact
Process and process zone COO
Product cost
Manufacturing cost
ESH impact on COO
ESH impact on factory costs
Capacity/cost analysis and optimization
Fault Isolation
New tool COO
Cost per measurement
Measurement impact on factory costs
Capacity and cost analysis
G Hz Operation
Manufacturing of systems
Manufacturing of systems
New Materials
Tools and process steps
Process sequences
Wafer fabrication and packaging
Part of COO
Bottleneck tool COO
Bottleneck tool impact on factory costs
Capacity/cost analysis and optimization
Research & Development
New equipment
New flow
New processes and integration
Equipment COO
Silicon process COO
Impact of material on manufacturing cost
Small Suppliers
Tool and material manufacturing COO
Tool and material manufacturing COO
Integrating tools and materials into user factories
Integrating tools and materials into user factories
Test equipment manufacturing
Test COO
Integrating Test operations
Yield Improvement
Equipment and material COO
Yield impact on factory costs
Yield impact on factory costs and operations


Note: Daren L. Dance is the yield model and defect budget team leader for the SIA National Technical Roadmap for Semiconductors.

1 The National Technology Roadmap for Semiconductors: 1997 Edition, L. Wilson, ed., Semiconductor Industry Association, San Jose, California

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